1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and, more particularly relates to a semiconductor device in which a short circuit between a contact electrode connected to a source region of a transistor and a contact electrode connected to a drain region of the transistor is prevented, and relates to a method of manufacturing the semiconductor device.
2. Description of Related Art
Many transistors are formed on a silicon substrate that constitutes a semiconductor device. Source regions and drain regions of these transistors are connected to wirings and elements on upper layers via various contact electrodes. For example, in a DRAM (Dynamic Random Access Memory) as one of representative semiconductor devices, one of a source region and a drain region of a cell transistor is connected to a bit line, and the other region is connected to a cell capacitor as a memory element (see Japanese Patent Application Laid-open No. 2007-287794).
FIG. 14 is a schematic cross-sectional view showing a general configuration of a memory cell of a DRAM.
As shown in FIG. 14, the memory cell of the DRAM includes a cell transistor 10 and a cell capacitor 20. The cell transistor 10 includes diffusion layers 11 and 12 one of which functions as a source region and the other functions as a drain region. When a voltage exceeding a threshold value is applied to a gate electrode 13, the diffusion layers 11 and 12 are electrically connected. The cell capacitor 20 includes a lower electrode 21, an upper electrode 22, and a capacitance insulating film 23 provided between these electrodes, and holds a charge based on data to be stored.
The diffusion layer 11 is connected to a bit line 30 via a cell contact 31 and a bit contact 32. On the other hand, the diffusion layer 12 is connected to the lower electrode 21 of the cell capacitor 20 via a cell contact 41 and a capacitance contact 42.
As shown in FIG. 14, the cell contacts 31 and 41 are contact electrodes embedded in an interlayer insulating film 51. An interlayer insulating film 52 is provided on the interlayer insulating film 51, and the bit contact 32 is embedded in the interlayer insulating film 52. Further, an interlayer insulating film 53 is provided on the interlayer insulating film 52, and the bit line 30 is embedded in the interlayer insulating film 53. The capacitance contact 42 is provided by penetrating through the Interlayer insulating films 52 and 53.
In a manufacturing process of the memory cell shown in FIG. 14, after the cell transistor 10 is formed before the cell capacitor 20 is formed, the cell contacts 31 and 41, the bit contact 32, the bit line 30, and the capacitance contact 42 are formed in this order. Because these steps are performed separately, misalignment inescapably occurs between the steps. Therefore, in the manufacturing process shown in FIG. 14, a margin for the bit contact 32 shrinks particularly in the formation of the capacitance contact 42, and there is a possibility that both are in contact.
This problem occurs for a reason such that, because an upper part of the bit contact 32 has a larger diameter, when high integration progresses, the distance between the upper part of the bit contact 32 and the capacitance contact 42 becomes very small.
While conventional problems have been explained above by taking a memory cell of a DRAM as an example, these problems can similarly occur to other semiconductor devices.